c1c4942eeb
They will be reused by the ast2600 driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org>
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Structures used by ASPEED clock drivers
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*
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* Copyright 2019 IBM Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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struct clk_div_table;
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struct regmap;
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/**
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* struct aspeed_gate_data - Aspeed gated clocks
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* @clock_idx: bit used to gate this clock in the clock register
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* @reset_idx: bit used to reset this IP in the reset register. -1 if no
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* reset is required when enabling the clock
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* @name: the clock name
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* @parent_name: the name of the parent clock
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* @flags: standard clock framework flags
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*/
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struct aspeed_gate_data {
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u8 clock_idx;
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s8 reset_idx;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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};
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/**
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* struct aspeed_clk_gate - Aspeed specific clk_gate structure
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register controlling gate
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* @clock_idx: bit used to gate this clock in the clock register
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* @reset_idx: bit used to reset this IP in the reset register. -1 if no
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* reset is required when enabling the clock
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* @flags: hardware-specific flags
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* @lock: register lock
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*
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* Some of the clocks in the Aspeed SoC must be put in reset before enabling.
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* This modified version of clk_gate allows an optional reset bit to be
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* specified.
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*/
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struct aspeed_clk_gate {
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struct clk_hw hw;
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struct regmap *map;
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u8 clock_idx;
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s8 reset_idx;
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u8 flags;
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spinlock_t *lock;
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};
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#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
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/**
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* struct aspeed_reset - Aspeed reset controller
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* @map: regmap to access the containing system controller
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* @rcdev: reset controller device
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*/
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struct aspeed_reset {
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struct regmap *map;
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struct reset_controller_dev rcdev;
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};
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#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
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/**
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* struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
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* @div_table: Common divider lookup table
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* @eclk_div_table: Divider lookup table for ECLK
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* @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
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* @calc_pll: Callback to maculate common PLL settings
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*/
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struct aspeed_clk_soc_data {
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const struct clk_div_table *div_table;
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const struct clk_div_table *eclk_div_table;
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const struct clk_div_table *mac_div_table;
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struct clk_hw *(*calc_pll)(const char *name, u32 val);
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};
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