2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
246 lines
6.5 KiB
C
246 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* DMA driver header for STMicroelectronics STi FDMA controller
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*
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* Copyright (C) 2014 STMicroelectronics
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*
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* Author: Ludovic Barre <Ludovic.barre@st.com>
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*/
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#ifndef __DMA_ST_FDMA_H
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#define __DMA_ST_FDMA_H
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#include <linux/dmaengine.h>
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#include <linux/dmapool.h>
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#include <linux/io.h>
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#include <linux/remoteproc/st_slim_rproc.h>
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#include "virt-dma.h"
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#define ST_FDMA_NR_DREQS 32
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#define FW_NAME_SIZE 30
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#define DRIVER_NAME "st-fdma"
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/**
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* struct st_fdma_generic_node - Free running/paced generic node
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*
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* @length: Length in bytes of a line in a 2D mem to mem
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* @sstride: Stride, in bytes, between source lines in a 2D data move
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* @dstride: Stride, in bytes, between destination lines in a 2D data move
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*/
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struct st_fdma_generic_node {
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u32 length;
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u32 sstride;
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u32 dstride;
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};
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/**
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* struct st_fdma_hw_node - Node structure used by fdma hw
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*
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* @next: Pointer to next node
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* @control: Transfer Control Parameters
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* @nbytes: Number of Bytes to read
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* @saddr: Source address
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* @daddr: Destination address
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*
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* @generic: generic node for free running/paced transfert type
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* 2 others transfert type are possible, but not yet implemented
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*
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* The NODE structures must be aligned to a 32 byte boundary
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*/
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struct st_fdma_hw_node {
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u32 next;
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u32 control;
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u32 nbytes;
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u32 saddr;
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u32 daddr;
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union {
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struct st_fdma_generic_node generic;
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};
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} __aligned(32);
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/*
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* node control parameters
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*/
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#define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)
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#define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN 0x0
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#define FDMA_NODE_CTRL_REQ_MAP_DREQ(n) ((n)&FDMA_NODE_CTRL_REQ_MAP_MASK)
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#define FDMA_NODE_CTRL_REQ_MAP_EXT FDMA_NODE_CTRL_REQ_MAP_MASK
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#define FDMA_NODE_CTRL_SRC_MASK GENMASK(6, 5)
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#define FDMA_NODE_CTRL_SRC_STATIC BIT(5)
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#define FDMA_NODE_CTRL_SRC_INCR BIT(6)
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#define FDMA_NODE_CTRL_DST_MASK GENMASK(8, 7)
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#define FDMA_NODE_CTRL_DST_STATIC BIT(7)
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#define FDMA_NODE_CTRL_DST_INCR BIT(8)
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#define FDMA_NODE_CTRL_SECURE BIT(15)
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#define FDMA_NODE_CTRL_PAUSE_EON BIT(30)
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#define FDMA_NODE_CTRL_INT_EON BIT(31)
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/**
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* struct st_fdma_sw_node - descriptor structure for link list
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*
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* @pdesc: Physical address of desc
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* @node: link used for putting this into a channel queue
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*/
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struct st_fdma_sw_node {
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dma_addr_t pdesc;
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struct st_fdma_hw_node *desc;
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};
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#define NAME_SZ 10
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struct st_fdma_driverdata {
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u32 id;
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char name[NAME_SZ];
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};
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struct st_fdma_desc {
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struct virt_dma_desc vdesc;
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struct st_fdma_chan *fchan;
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bool iscyclic;
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unsigned int n_nodes;
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struct st_fdma_sw_node node[];
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};
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enum st_fdma_type {
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ST_FDMA_TYPE_FREE_RUN,
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ST_FDMA_TYPE_PACED,
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};
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struct st_fdma_cfg {
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struct device_node *of_node;
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enum st_fdma_type type;
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dma_addr_t dev_addr;
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enum dma_transfer_direction dir;
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int req_line; /* request line */
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long req_ctrl; /* Request control */
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};
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struct st_fdma_chan {
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struct st_fdma_dev *fdev;
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struct dma_pool *node_pool;
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struct dma_slave_config scfg;
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struct st_fdma_cfg cfg;
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int dreq_line;
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struct virt_dma_chan vchan;
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struct st_fdma_desc *fdesc;
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enum dma_status status;
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};
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struct st_fdma_dev {
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struct device *dev;
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const struct st_fdma_driverdata *drvdata;
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struct dma_device dma_device;
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struct st_slim_rproc *slim_rproc;
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int irq;
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struct st_fdma_chan *chans;
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spinlock_t dreq_lock;
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unsigned long dreq_mask;
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u32 nr_channels;
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char fw_name[FW_NAME_SIZE];
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};
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/* Peripheral Registers*/
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#define FDMA_CMD_STA_OFST 0xFC0
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#define FDMA_CMD_SET_OFST 0xFC4
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#define FDMA_CMD_CLR_OFST 0xFC8
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#define FDMA_CMD_MASK_OFST 0xFCC
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#define FDMA_CMD_START(ch) (0x1 << (ch << 1))
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#define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1))
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#define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1))
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#define FDMA_INT_STA_OFST 0xFD0
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#define FDMA_INT_STA_CH 0x1
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#define FDMA_INT_STA_ERR 0x2
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#define FDMA_INT_SET_OFST 0xFD4
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#define FDMA_INT_CLR_OFST 0xFD8
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#define FDMA_INT_MASK_OFST 0xFDC
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#define fdma_read(fdev, name) \
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readl((fdev)->slim_rproc->peri + name)
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#define fdma_write(fdev, val, name) \
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writel((val), (fdev)->slim_rproc->peri + name)
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/* fchan interface (dmem) */
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#define FDMA_CH_CMD_OFST 0x200
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#define FDMA_CH_CMD_STA_MASK GENMASK(1, 0)
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#define FDMA_CH_CMD_STA_IDLE (0x0)
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#define FDMA_CH_CMD_STA_START (0x1)
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#define FDMA_CH_CMD_STA_RUNNING (0x2)
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#define FDMA_CH_CMD_STA_PAUSED (0x3)
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#define FDMA_CH_CMD_ERR_MASK GENMASK(4, 2)
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#define FDMA_CH_CMD_ERR_INT (0x0 << 2)
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#define FDMA_CH_CMD_ERR_NAND (0x1 << 2)
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#define FDMA_CH_CMD_ERR_MCHI (0x2 << 2)
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#define FDMA_CH_CMD_DATA_MASK GENMASK(31, 5)
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#define fchan_read(fchan, name) \
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readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
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+ (fchan)->vchan.chan.chan_id * 0x4 \
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+ name)
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#define fchan_write(fchan, val, name) \
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writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
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+ (fchan)->vchan.chan.chan_id * 0x4 \
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+ name)
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/* req interface */
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#define FDMA_REQ_CTRL_OFST 0x240
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#define dreq_write(fchan, val, name) \
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writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
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+ fchan->dreq_line * 0x04 \
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+ name)
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/* node interface */
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#define FDMA_NODE_SZ 128
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#define FDMA_PTRN_OFST 0x800
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#define FDMA_CNTN_OFST 0x808
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#define FDMA_SADDRN_OFST 0x80c
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#define FDMA_DADDRN_OFST 0x810
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#define fnode_read(fchan, name) \
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readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
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+ (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
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+ name)
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#define fnode_write(fchan, val, name) \
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writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
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+ (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
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+ name)
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/*
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* request control bits
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*/
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#define FDMA_REQ_CTRL_NUM_OPS_MASK GENMASK(31, 24)
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#define FDMA_REQ_CTRL_NUM_OPS(n) (FDMA_REQ_CTRL_NUM_OPS_MASK & \
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((n) << 24))
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#define FDMA_REQ_CTRL_INITIATOR_MASK BIT(22)
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#define FDMA_REQ_CTRL_INIT0 (0x0 << 22)
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#define FDMA_REQ_CTRL_INIT1 (0x1 << 22)
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#define FDMA_REQ_CTRL_INC_ADDR_ON BIT(21)
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#define FDMA_REQ_CTRL_DATA_SWAP_ON BIT(17)
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#define FDMA_REQ_CTRL_WNR BIT(14)
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#define FDMA_REQ_CTRL_OPCODE_MASK GENMASK(7, 4)
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#define FDMA_REQ_CTRL_OPCODE_LD_ST1 (0x0 << 4)
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#define FDMA_REQ_CTRL_OPCODE_LD_ST2 (0x1 << 4)
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#define FDMA_REQ_CTRL_OPCODE_LD_ST4 (0x2 << 4)
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#define FDMA_REQ_CTRL_OPCODE_LD_ST8 (0x3 << 4)
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#define FDMA_REQ_CTRL_OPCODE_LD_ST16 (0x4 << 4)
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#define FDMA_REQ_CTRL_OPCODE_LD_ST32 (0x5 << 4)
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#define FDMA_REQ_CTRL_OPCODE_LD_ST64 (0x6 << 4)
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#define FDMA_REQ_CTRL_HOLDOFF_MASK GENMASK(2, 0)
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#define FDMA_REQ_CTRL_HOLDOFF(n) ((n) & FDMA_REQ_CTRL_HOLDOFF_MASK)
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/* bits used by client to configure request control */
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#define FDMA_REQ_CTRL_CFG_MASK (FDMA_REQ_CTRL_HOLDOFF_MASK | \
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FDMA_REQ_CTRL_DATA_SWAP_ON | \
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FDMA_REQ_CTRL_INC_ADDR_ON | \
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FDMA_REQ_CTRL_INITIATOR_MASK)
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#endif /* __DMA_ST_FDMA_H */
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