f735261baa
This patch adds a check on avivo chips to see if we are in the VBL region for the active crtcs when we trigger the engine change. I appear to have glitches locally on pm transistion (not sure all fixes are in yet) and this at least seems to be correct here, maybe others can test on systems with no glitches.
63 lines
2.4 KiB
C
63 lines
2.4 KiB
C
/*
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* Copyright 2009 Advanced Micro Devices, Inc.
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* Copyright 2009 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef AVIVOD_H
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#define AVIVOD_H
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#define D1CRTC_CONTROL 0x6080
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#define CRTC_EN (1 << 0)
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#define D1CRTC_STATUS 0x609c
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#define D1CRTC_UPDATE_LOCK 0x60E8
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#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
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#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
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#define D2CRTC_CONTROL 0x6880
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#define D2CRTC_STATUS 0x689c
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#define D2CRTC_UPDATE_LOCK 0x68E8
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#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
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#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
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#define D1VGA_CONTROL 0x0330
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#define DVGA_CONTROL_MODE_ENABLE (1 << 0)
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#define DVGA_CONTROL_TIMING_SELECT (1 << 8)
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#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
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#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
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#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
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#define DVGA_CONTROL_ROTATE (1 << 24)
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#define D2VGA_CONTROL 0x0338
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#define VGA_HDP_CONTROL 0x328
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#define VGA_MEM_PAGE_SELECT_EN (1 << 0)
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#define VGA_MEMORY_DISABLE (1 << 4)
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#define VGA_RBBM_LOCK_DISABLE (1 << 8)
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#define VGA_SOFT_RESET (1 << 16)
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#define VGA_MEMORY_BASE_ADDRESS 0x0310
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#define VGA_RENDER_CONTROL 0x0300
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#define VGA_VSTATUS_CNTL_MASK 0x00030000
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#endif
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