fd67e9c6ed
The Tegra DRM driver heavily relies on the implementations for runtime suspend/resume to be called at specific times. Unfortunately, there are some cases where that doesn't work. One example is if the user disables runtime PM for a given subdevice. Another example is that the PM core acquires a reference to runtime PM during system sleep, effectively preventing devices from going into low power modes. This is intentional to avoid nasty race conditions, but it also causes system sleep to not function properly on all Tegra systems. Fix this by not implementing runtime PM at all. Instead, a minimal, reference-counted suspend/resume infrastructure is added to the host1x bus. This has the benefit that it can be used regardless of the system power state (or any transitions we might be in), or whether or not the user allows runtime PM. Atomic modesetting guarantees that these functions will end up being called at the right point in time, so the pitfalls for the more generic runtime PM do not apply here. Signed-off-by: Thierry Reding <treding@nvidia.com>
99 lines
2.2 KiB
C
99 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef TEGRA_HUB_H
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#define TEGRA_HUB_H 1
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#include <drm/drm_plane.h>
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#include "plane.h"
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struct tegra_dc;
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struct tegra_windowgroup {
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unsigned int usecount;
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struct mutex lock;
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unsigned int index;
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struct host1x_client *parent;
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struct reset_control *rst;
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};
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struct tegra_shared_plane {
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struct tegra_plane base;
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struct tegra_windowgroup *wgrp;
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};
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static inline struct tegra_shared_plane *
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to_tegra_shared_plane(struct drm_plane *plane)
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{
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return container_of(plane, struct tegra_shared_plane, base.base);
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}
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struct tegra_display_hub_soc {
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unsigned int num_wgrps;
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bool supports_dsc;
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};
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struct tegra_display_hub {
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struct drm_private_obj base;
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struct host1x_client client;
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struct clk *clk_disp;
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struct clk *clk_dsc;
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struct clk *clk_hub;
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struct reset_control *rst;
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unsigned int num_heads;
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struct clk **clk_heads;
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const struct tegra_display_hub_soc *soc;
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struct tegra_windowgroup *wgrps;
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};
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static inline struct tegra_display_hub *
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to_tegra_display_hub(struct host1x_client *client)
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{
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return container_of(client, struct tegra_display_hub, client);
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}
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struct tegra_display_hub_state {
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struct drm_private_state base;
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struct tegra_dc *dc;
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unsigned long rate;
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struct clk *clk;
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};
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static inline struct tegra_display_hub_state *
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to_tegra_display_hub_state(struct drm_private_state *priv)
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{
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return container_of(priv, struct tegra_display_hub_state, base);
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}
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struct tegra_dc;
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struct tegra_plane;
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int tegra_display_hub_prepare(struct tegra_display_hub *hub);
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void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
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struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
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struct tegra_dc *dc,
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unsigned int wgrp,
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unsigned int index);
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int tegra_display_hub_atomic_check(struct drm_device *drm,
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struct drm_atomic_state *state);
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void tegra_display_hub_atomic_commit(struct drm_device *drm,
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struct drm_atomic_state *state);
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#define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
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#define LATENCY_EVENT (1 << 3)
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#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
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#define CURS_SLOTS(x) (((x) & 0xff) << 8)
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#define WGRP_SLOTS(x) (((x) & 0xff) << 0)
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#endif /* TEGRA_HUB_H */
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