7d32358be8
"xargs echo" is not a safe way to remove line breaks because the input may exceed the command line limit and xargs may break it up into multiple invocations of echo. This should never happen because scripts/gen_autoksyms.sh expects all undefined symbols are placed in the second line of .mod files. One possible way is to replace "xargs echo" with "sed ':x;N;$!bx;s/\n/ /g'" or something, but I rewrote the code by using awk because it is more readable. This issue was reported by Sami Tolvanen; in his Clang LTO patch set, $(multi-used-m) is no longer an ELF object, but a thin archive that contains LLVM bitcode files. llvm-nm prints out symbols for each archive member separately, which results a lot of dupications, in some places, beyond the system-defined limit. This problem must be fixed irrespective of LTO, and we must ensure zero possibility of having this issue. Link: https://lkml.org/lkml/2020/12/1/1658 Reported-by: Sami Tolvanen <samitolvanen@google.com> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Sami Tolvanen <samitolvanen@google.com>
527 lines
17 KiB
Makefile
527 lines
17 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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# ==========================================================================
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# Building
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# ==========================================================================
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src := $(obj)
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PHONY := __build
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__build:
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# Init all relevant variables used in kbuild files so
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# 1) they have correct type
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# 2) they do not inherit any value from the environment
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obj-y :=
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obj-m :=
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lib-y :=
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lib-m :=
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always :=
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always-y :=
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always-m :=
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targets :=
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subdir-y :=
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subdir-m :=
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EXTRA_AFLAGS :=
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EXTRA_CFLAGS :=
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EXTRA_CPPFLAGS :=
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EXTRA_LDFLAGS :=
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asflags-y :=
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ccflags-y :=
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cppflags-y :=
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ldflags-y :=
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subdir-asflags-y :=
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subdir-ccflags-y :=
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# Read auto.conf if it exists, otherwise ignore
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-include include/config/auto.conf
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include scripts/Kbuild.include
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# The filename Kbuild has precedence over Makefile
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kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
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kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
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include $(kbuild-file)
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include scripts/Makefile.lib
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# Do not include hostprogs rules unless needed.
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# $(sort ...) is used here to remove duplicated words and excessive spaces.
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hostprogs := $(sort $(hostprogs))
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ifneq ($(hostprogs),)
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include scripts/Makefile.host
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endif
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# Do not include userprogs rules unless needed.
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# $(sort ...) is used here to remove duplicated words and excessive spaces.
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userprogs := $(sort $(userprogs))
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ifneq ($(userprogs),)
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include scripts/Makefile.userprogs
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endif
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ifndef obj
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$(warning kbuild: Makefile.build is included improperly)
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endif
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ifeq ($(need-modorder),)
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ifneq ($(obj-m),)
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$(warning $(patsubst %.o,'%.ko',$(obj-m)) will not be built even though obj-m is specified.)
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$(warning You cannot use subdir-y/m to visit a module Makefile. Use obj-y/m instead.)
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endif
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endif
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# ===========================================================================
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# subdir-builtin and subdir-modorder may contain duplications. Use $(sort ...)
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subdir-builtin := $(sort $(filter %/built-in.a, $(real-obj-y)))
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subdir-modorder := $(sort $(filter %/modules.order, $(obj-m)))
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targets-for-builtin := $(extra-y)
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ifneq ($(strip $(lib-y) $(lib-m) $(lib-)),)
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targets-for-builtin += $(obj)/lib.a
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endif
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ifdef need-builtin
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targets-for-builtin += $(obj)/built-in.a
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endif
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targets-for-modules := $(patsubst %.o, %.mod, $(filter %.o, $(obj-m)))
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ifdef need-modorder
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targets-for-modules += $(obj)/modules.order
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endif
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targets += $(targets-for-builtin) $(targets-for-modules)
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# Linus' kernel sanity checking tool
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ifeq ($(KBUILD_CHECKSRC),1)
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quiet_cmd_checksrc = CHECK $<
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cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $<
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else ifeq ($(KBUILD_CHECKSRC),2)
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quiet_cmd_force_checksrc = CHECK $<
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cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $<
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endif
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ifneq ($(KBUILD_EXTRA_WARN),)
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cmd_checkdoc = $(srctree)/scripts/kernel-doc -none $<
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endif
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# Compile C sources (.c)
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# ---------------------------------------------------------------------------
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quiet_cmd_cc_s_c = CC $(quiet_modtag) $@
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cmd_cc_s_c = $(CC) $(filter-out $(DEBUG_CFLAGS), $(c_flags)) -fverbose-asm -S -o $@ $<
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$(obj)/%.s: $(src)/%.c FORCE
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$(call if_changed_dep,cc_s_c)
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quiet_cmd_cpp_i_c = CPP $(quiet_modtag) $@
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cmd_cpp_i_c = $(CPP) $(c_flags) -o $@ $<
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$(obj)/%.i: $(src)/%.c FORCE
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$(call if_changed_dep,cpp_i_c)
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# These mirror gensymtypes_S and co below, keep them in synch.
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cmd_gensymtypes_c = \
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$(CPP) -D__GENKSYMS__ $(c_flags) $< | \
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scripts/genksyms/genksyms $(if $(1), -T $(2)) \
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$(patsubst y,-R,$(CONFIG_MODULE_REL_CRCS)) \
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$(if $(KBUILD_PRESERVE),-p) \
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-r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null))
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quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@
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cmd_cc_symtypes_c = \
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$(call cmd_gensymtypes_c,true,$@) >/dev/null; \
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test -s $@ || rm -f $@
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$(obj)/%.symtypes : $(src)/%.c FORCE
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$(call cmd,cc_symtypes_c)
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# LLVM assembly
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# Generate .ll files from .c
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quiet_cmd_cc_ll_c = CC $(quiet_modtag) $@
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cmd_cc_ll_c = $(CC) $(c_flags) -emit-llvm -S -o $@ $<
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$(obj)/%.ll: $(src)/%.c FORCE
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$(call if_changed_dep,cc_ll_c)
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# C (.c) files
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# The C file is compiled and updated dependency information is generated.
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# (See cmd_cc_o_c + relevant part of rule_cc_o_c)
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quiet_cmd_cc_o_c = CC $(quiet_modtag) $@
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cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
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ifdef CONFIG_MODVERSIONS
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# When module versioning is enabled the following steps are executed:
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# o compile a <file>.o from <file>.c
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# o if <file>.o doesn't contain a __ksymtab version, i.e. does
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# not export symbols, it's done.
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# o otherwise, we calculate symbol versions using the good old
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# genksyms on the preprocessed source and postprocess them in a way
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# that they are usable as a linker script
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# o generate .tmp_<file>.o from <file>.o using the linker to
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# replace the unresolved symbols __crc_exported_symbol with
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# the actual value of the checksum generated by genksyms
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# o remove .tmp_<file>.o to <file>.o
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cmd_modversions_c = \
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if $(OBJDUMP) -h $@ | grep -q __ksymtab; then \
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$(call cmd_gensymtypes_c,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \
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> $(@D)/.tmp_$(@F:.o=.ver); \
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\
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$(LD) $(KBUILD_LDFLAGS) -r -o $(@D)/.tmp_$(@F) $@ \
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-T $(@D)/.tmp_$(@F:.o=.ver); \
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mv -f $(@D)/.tmp_$(@F) $@; \
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rm -f $(@D)/.tmp_$(@F:.o=.ver); \
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fi
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endif
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ifdef CONFIG_FTRACE_MCOUNT_RECORD
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ifndef CC_USING_RECORD_MCOUNT
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# compiler will not generate __mcount_loc use recordmcount or recordmcount.pl
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ifdef BUILD_C_RECORDMCOUNT
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ifeq ("$(origin RECORDMCOUNT_WARN)", "command line")
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RECORDMCOUNT_FLAGS = -w
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endif
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# Due to recursion, we must skip empty.o.
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# The empty.o file is created in the make process in order to determine
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# the target endianness and word size. It is made before all other C
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# files, including recordmcount.
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sub_cmd_record_mcount = \
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if [ $(@) != "scripts/mod/empty.o" ]; then \
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$(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)"; \
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fi;
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recordmcount_source := $(srctree)/scripts/recordmcount.c \
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$(srctree)/scripts/recordmcount.h
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else
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sub_cmd_record_mcount = perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \
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"$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \
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"$(if $(CONFIG_64BIT),64,32)" \
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"$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS)" \
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"$(LD) $(KBUILD_LDFLAGS)" "$(NM)" "$(RM)" "$(MV)" \
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"$(if $(part-of-module),1,0)" "$(@)";
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recordmcount_source := $(srctree)/scripts/recordmcount.pl
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endif # BUILD_C_RECORDMCOUNT
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cmd_record_mcount = $(if $(findstring $(strip $(CC_FLAGS_FTRACE)),$(_c_flags)), \
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$(sub_cmd_record_mcount))
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endif # CC_USING_RECORD_MCOUNT
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endif # CONFIG_FTRACE_MCOUNT_RECORD
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ifdef CONFIG_STACK_VALIDATION
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ifneq ($(SKIP_STACK_VALIDATION),1)
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__objtool_obj := $(objtree)/tools/objtool/objtool
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objtool_args = $(if $(CONFIG_UNWINDER_ORC),orc generate,check)
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objtool_args += $(if $(part-of-module), --module,)
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ifndef CONFIG_FRAME_POINTER
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objtool_args += --no-fp
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endif
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ifdef CONFIG_GCOV_KERNEL
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objtool_args += --no-unreachable
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endif
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ifdef CONFIG_RETPOLINE
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objtool_args += --retpoline
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endif
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ifdef CONFIG_X86_SMAP
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objtool_args += --uaccess
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endif
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# 'OBJECT_FILES_NON_STANDARD := y': skip objtool checking for a directory
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# 'OBJECT_FILES_NON_STANDARD_foo.o := 'y': skip objtool checking for a file
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# 'OBJECT_FILES_NON_STANDARD_foo.o := 'n': override directory skip for a file
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cmd_objtool = $(if $(patsubst y%,, \
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$(OBJECT_FILES_NON_STANDARD_$(basetarget).o)$(OBJECT_FILES_NON_STANDARD)n), \
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$(__objtool_obj) $(objtool_args) $@)
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objtool_obj = $(if $(patsubst y%,, \
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$(OBJECT_FILES_NON_STANDARD_$(basetarget).o)$(OBJECT_FILES_NON_STANDARD)n), \
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$(__objtool_obj))
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endif # SKIP_STACK_VALIDATION
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endif # CONFIG_STACK_VALIDATION
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# Rebuild all objects when objtool changes, or is enabled/disabled.
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objtool_dep = $(objtool_obj) \
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$(wildcard include/config/orc/unwinder.h \
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include/config/stack/validation.h)
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ifdef CONFIG_TRIM_UNUSED_KSYMS
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cmd_gen_ksymdeps = \
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$(CONFIG_SHELL) $(srctree)/scripts/gen_ksymdeps.sh $@ >> $(dot-target).cmd
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# List module undefined symbols
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undefined_syms = $(NM) $< | $(AWK) '$$1 == "U" { printf("%s%s", x++ ? " " : "", $$2) }';
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endif
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define rule_cc_o_c
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$(call cmd_and_fixdep,cc_o_c)
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$(call cmd,gen_ksymdeps)
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$(call cmd,checksrc)
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$(call cmd,checkdoc)
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$(call cmd,objtool)
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$(call cmd,modversions_c)
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$(call cmd,record_mcount)
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endef
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define rule_as_o_S
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$(call cmd_and_fixdep,as_o_S)
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$(call cmd,gen_ksymdeps)
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$(call cmd,objtool)
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$(call cmd,modversions_S)
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endef
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# Built-in and composite module parts
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$(obj)/%.o: $(src)/%.c $(recordmcount_source) $(objtool_dep) FORCE
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$(call if_changed_rule,cc_o_c)
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$(call cmd,force_checksrc)
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cmd_mod = { \
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echo $(if $($*-objs)$($*-y)$($*-m), $(addprefix $(obj)/, $($*-objs) $($*-y) $($*-m)), $(@:.mod=.o)); \
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$(undefined_syms) echo; \
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} > $@
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$(obj)/%.mod: $(obj)/%.o FORCE
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$(call if_changed,mod)
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quiet_cmd_cc_lst_c = MKLST $@
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cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \
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$(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \
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System.map $(OBJDUMP) > $@
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$(obj)/%.lst: $(src)/%.c FORCE
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$(call if_changed_dep,cc_lst_c)
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# Compile assembler sources (.S)
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# ---------------------------------------------------------------------------
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# .S file exports must have their C prototypes defined in asm/asm-prototypes.h
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# or a file that it includes, in order to get versioned symbols. We build a
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# dummy C file that includes asm-prototypes and the EXPORT_SYMBOL lines from
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# the .S file (with trailing ';'), and run genksyms on that, to extract vers.
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#
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# This is convoluted. The .S file must first be preprocessed to run guards and
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# expand names, then the resulting exports must be constructed into plain
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# EXPORT_SYMBOL(symbol); to build our dummy C file, and that gets preprocessed
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# to make the genksyms input.
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#
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# These mirror gensymtypes_c and co above, keep them in synch.
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cmd_gensymtypes_S = \
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{ echo "\#include <linux/kernel.h>" ; \
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echo "\#include <asm/asm-prototypes.h>" ; \
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$(CPP) $(a_flags) $< | \
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grep "\<___EXPORT_SYMBOL\>" | \
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sed 's/.*___EXPORT_SYMBOL[[:space:]]*\([a-zA-Z0-9_]*\)[[:space:]]*,.*/EXPORT_SYMBOL(\1);/' ; } | \
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$(CPP) -D__GENKSYMS__ $(c_flags) -xc - | \
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scripts/genksyms/genksyms $(if $(1), -T $(2)) \
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$(patsubst y,-R,$(CONFIG_MODULE_REL_CRCS)) \
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$(if $(KBUILD_PRESERVE),-p) \
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-r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null))
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quiet_cmd_cc_symtypes_S = SYM $(quiet_modtag) $@
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cmd_cc_symtypes_S = \
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$(call cmd_gensymtypes_S,true,$@) >/dev/null; \
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test -s $@ || rm -f $@
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$(obj)/%.symtypes : $(src)/%.S FORCE
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$(call cmd,cc_symtypes_S)
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quiet_cmd_cpp_s_S = CPP $(quiet_modtag) $@
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cmd_cpp_s_S = $(CPP) $(a_flags) -o $@ $<
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$(obj)/%.s: $(src)/%.S FORCE
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$(call if_changed_dep,cpp_s_S)
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quiet_cmd_as_o_S = AS $(quiet_modtag) $@
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cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $<
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ifdef CONFIG_ASM_MODVERSIONS
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# versioning matches the C process described above, with difference that
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# we parse asm-prototypes.h C header to get function definitions.
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cmd_modversions_S = \
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if $(OBJDUMP) -h $@ | grep -q __ksymtab; then \
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$(call cmd_gensymtypes_S,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \
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> $(@D)/.tmp_$(@F:.o=.ver); \
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\
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$(LD) $(KBUILD_LDFLAGS) -r -o $(@D)/.tmp_$(@F) $@ \
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-T $(@D)/.tmp_$(@F:.o=.ver); \
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mv -f $(@D)/.tmp_$(@F) $@; \
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rm -f $(@D)/.tmp_$(@F:.o=.ver); \
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fi
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endif
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$(obj)/%.o: $(src)/%.S $(objtool_dep) FORCE
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$(call if_changed_rule,as_o_S)
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targets += $(filter-out $(subdir-builtin), $(real-obj-y))
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targets += $(filter-out $(subdir-modorder), $(real-obj-m))
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targets += $(lib-y) $(always-y) $(MAKECMDGOALS)
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# Linker scripts preprocessor (.lds.S -> .lds)
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# ---------------------------------------------------------------------------
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quiet_cmd_cpp_lds_S = LDS $@
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cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \
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-D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
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$(obj)/%.lds: $(src)/%.lds.S FORCE
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$(call if_changed_dep,cpp_lds_S)
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# ASN.1 grammar
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# ---------------------------------------------------------------------------
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quiet_cmd_asn1_compiler = ASN.1 $(basename $@).[ch]
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cmd_asn1_compiler = $(objtree)/scripts/asn1_compiler $< \
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$(basename $@).c $(basename $@).h
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$(obj)/%.asn1.c $(obj)/%.asn1.h: $(src)/%.asn1 $(objtree)/scripts/asn1_compiler
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$(call cmd,asn1_compiler)
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|
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# Build the compiled-in targets
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|
# ---------------------------------------------------------------------------
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|
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# To build objects in subdirs, we need to descend into the directories
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$(subdir-builtin): $(obj)/%/built-in.a: $(obj)/% ;
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$(subdir-modorder): $(obj)/%/modules.order: $(obj)/% ;
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#
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# Rule to compile a set of .o files into one .a file (without symbol table)
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#
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quiet_cmd_ar_builtin = AR $@
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cmd_ar_builtin = rm -f $@; $(AR) cDPrST $@ $(real-prereqs)
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$(obj)/built-in.a: $(real-obj-y) FORCE
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$(call if_changed,ar_builtin)
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#
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# Rule to create modules.order file
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#
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# Create commands to either record .ko file or cat modules.order from
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# a subdirectory
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# Add $(obj-m) as the prerequisite to avoid updating the timestamp of
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# modules.order unless contained modules are updated.
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cmd_modules_order = { $(foreach m, $(real-prereqs), \
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$(if $(filter %/modules.order, $m), cat $m, echo $(patsubst %.o,%.ko,$m));) :; } \
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| $(AWK) '!x[$$0]++' - > $@
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|
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$(obj)/modules.order: $(obj-m) FORCE
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|
$(call if_changed,modules_order)
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|
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#
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# Rule to compile a set of .o files into one .a file (with symbol table)
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|
#
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$(obj)/lib.a: $(lib-y) FORCE
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$(call if_changed,ar)
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|
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# NOTE:
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# Do not replace $(filter %.o,^) with $(real-prereqs). When a single object
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# module is turned into a multi object module, $^ will contain header file
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|
# dependencies recorded in the .*.cmd file.
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quiet_cmd_link_multi-m = LD [M] $@
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cmd_link_multi-m = $(LD) $(ld_flags) -r -o $@ $(filter %.o,$^)
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|
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$(multi-used-m): FORCE
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$(call if_changed,link_multi-m)
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$(call multi_depend, $(multi-used-m), .o, -objs -y -m)
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targets += $(multi-used-m)
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targets := $(filter-out $(PHONY), $(targets))
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|
|
# Add intermediate targets:
|
|
# When building objects with specific suffix patterns, add intermediate
|
|
# targets that the final targets are derived from.
|
|
intermediate_targets = $(foreach sfx, $(2), \
|
|
$(patsubst %$(strip $(1)),%$(sfx), \
|
|
$(filter %$(strip $(1)), $(targets))))
|
|
# %.asn1.o <- %.asn1.[ch] <- %.asn1
|
|
# %.dtb.o <- %.dtb.S <- %.dtb <- %.dts
|
|
# %.lex.o <- %.lex.c <- %.l
|
|
# %.tab.o <- %.tab.[ch] <- %.y
|
|
targets += $(call intermediate_targets, .asn1.o, .asn1.c .asn1.h) \
|
|
$(call intermediate_targets, .dtb.o, .dtb.S .dtb) \
|
|
$(call intermediate_targets, .lex.o, .lex.c) \
|
|
$(call intermediate_targets, .tab.o, .tab.c .tab.h)
|
|
|
|
# Build
|
|
# ---------------------------------------------------------------------------
|
|
|
|
ifdef single-build
|
|
|
|
KBUILD_SINGLE_TARGETS := $(filter $(obj)/%, $(KBUILD_SINGLE_TARGETS))
|
|
|
|
curdir-single := $(sort $(foreach x, $(KBUILD_SINGLE_TARGETS), \
|
|
$(if $(filter $(x) $(basename $(x)).o, $(targets)), $(x))))
|
|
|
|
# Handle single targets without any rule: show "Nothing to be done for ..." or
|
|
# "No rule to make target ..." depending on whether the target exists.
|
|
unknown-single := $(filter-out $(addsuffix /%, $(subdir-ym)), \
|
|
$(filter-out $(curdir-single), $(KBUILD_SINGLE_TARGETS)))
|
|
|
|
single-subdirs := $(foreach d, $(subdir-ym), \
|
|
$(if $(filter $(d)/%, $(KBUILD_SINGLE_TARGETS)), $(d)))
|
|
|
|
__build: $(curdir-single) $(single-subdirs)
|
|
ifneq ($(unknown-single),)
|
|
$(Q)$(MAKE) -f /dev/null $(unknown-single)
|
|
endif
|
|
@:
|
|
|
|
ifeq ($(curdir-single),)
|
|
# Nothing to do in this directory. Do not include any .*.cmd file for speed-up
|
|
targets :=
|
|
else
|
|
targets += $(curdir-single)
|
|
endif
|
|
|
|
else
|
|
|
|
__build: $(if $(KBUILD_BUILTIN), $(targets-for-builtin)) \
|
|
$(if $(KBUILD_MODULES), $(targets-for-modules)) \
|
|
$(subdir-ym) $(always-y)
|
|
@:
|
|
|
|
endif
|
|
|
|
# Descending
|
|
# ---------------------------------------------------------------------------
|
|
|
|
PHONY += $(subdir-ym)
|
|
$(subdir-ym):
|
|
$(Q)$(MAKE) $(build)=$@ \
|
|
$(if $(filter $@/, $(KBUILD_SINGLE_TARGETS)),single-build=) \
|
|
need-builtin=$(if $(filter $@/built-in.a, $(subdir-builtin)),1) \
|
|
need-modorder=$(if $(filter $@/modules.order, $(subdir-modorder)),1)
|
|
|
|
# Add FORCE to the prequisites of a target to force it to be always rebuilt.
|
|
# ---------------------------------------------------------------------------
|
|
|
|
PHONY += FORCE
|
|
|
|
FORCE:
|
|
|
|
# Read all saved command lines and dependencies for the $(targets) we
|
|
# may be building above, using $(if_changed{,_dep}). As an
|
|
# optimization, we don't need to read them if the target does not
|
|
# exist, we will rebuild anyway in that case.
|
|
|
|
existing-targets := $(wildcard $(sort $(targets)))
|
|
|
|
-include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)
|
|
|
|
# Create directories for object files if they do not exist
|
|
obj-dirs := $(sort $(patsubst %/,%, $(dir $(targets))))
|
|
# If targets exist, their directories apparently exist. Skip mkdir.
|
|
existing-dirs := $(sort $(patsubst %/,%, $(dir $(existing-targets))))
|
|
obj-dirs := $(strip $(filter-out $(existing-dirs), $(obj-dirs)))
|
|
ifneq ($(obj-dirs),)
|
|
$(shell mkdir -p $(obj-dirs))
|
|
endif
|
|
|
|
.PHONY: $(PHONY)
|